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| 56F807 Data Sheet Preliminary Technical Data 56F800 16-bit Digital Signal Controllers DSP56F807 Rev. 15 01/2007 freescale.com 56F807 General Description * * * * Up to 40 MIPS at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture Hardware DO and REP loops MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 60K x 16-bit words (120KB) Program Flash 2K x 16-bit words (4KB) Program RAM 8K x 16-bit words (16KB) Data Flash 4K x 16-bit words (8KB) Data RAM 2K x 16-bit words (4KB) Boot Flash Up to 64K x 16- bit words (128KB) each of external Program and Data memory * * * * * * * * * * Two 6 channel PWM Modules Four 4 channel, 12-bit ADCs Two Quadrature Decoders CAN 2.0 B Module Two Serial Communication Interfaces (SCIs) Serial Peripheral Interface (SPI) Up to four General Purpose Quad Timers JTAG/OnCETM port for debugging 14 Dedicated and 18 Shared GPIO lines 160-pin LQFP or 160 MAPBGA Packages * * * * * * 6 3 4 6 PWM Outputs Current Sense Inputs Fault Inputs PWM Outputs Current Sense Inputs Fault Inputs A/D1 A/D2 A/D1 A/D2 ADCA VREF ADCB VREF2 PWMA RSTO RESET IRQA EXTBOOT IRQB 6 JTAG/ OnCE Port VPP VCAPC VDD 2 8 VSS 10* Digital Reg VDDA 3 VSSA 3 Analog Reg PWMB 3 4 4 4 4 4 Low Voltage Supervisor 4 Quadrature Decoder 0 /Quad Timer Quadrature Decoder 1 /Quad Timer B Quad Timer C Interrupt Controller Program Controller and Hardware Looping Unit Address Generation Unit Data ALU 16 x 16 + 36 36-Bit MAC Three 16-bit Input Registers Two 36-bit Accumulators Bit Manipulation Unit 4 2 4 2 2 Program Memory 61440 x 16 Flash 2048 x 16 SRAM Boot Flash 2048 x 16 Flash Data Memory 8192 x 16 Flash 4096 x 16 SRAM * PAB * * PDB * * * * IPBB CONTROLS 16 PLL CLKO Quad Timer D / Alt Func CAN 2.0A/B SCI0 or GPIO SCI1 or GPIO SPI or GPIO Dedicated GPIO XDB2 CGDB XAB1 XAB2 16-Bit 56800 Core XTAL Clock Gen EXTAL * INTERRUPT CONTROLS 16 COP/ Watchdog COP RESET MODULE CONTROLS ADDRESS BUS [8:0] DATA BUS [15:0] 2 4 14 Application-Specific Memory & Peripherals IPBus Bridge (IPBB) External Bus Interface Unit External Address Bus Switch External Data Bus Switch Bus Control A[00:05] 6 10 16 PS Select DS Select WR Enable RD Enable A[06:15] or GPIO-E2:E3 & GPIO-A0:A7 D[00:15] *includes TCS pin which is reserved for factory use and is tied to VSS 56F807 Block Diagram 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 3 Part 1 Overview 1.1 56F807 Features 1.1.1 * * * * * * * * * * * * * * Processing Core Efficient 16-bit 56800 family controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 x 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique processor addressing modes Hardware DO and REP loops Three internal address buses and one external address bus Four internal data buses and one external data bus Instruction set supports both DSP and controller functions Controller style addressing modes and instructions for compact code Efficient C compiler and local variable support Software subroutine and interrupt stack with depth limited only by memory JTAG/OnCE debug programming interface 1.1.2 * * Memory Harvard architecture permits as many as three simultaneous accesses to Program and Data memory On-chip memory including a low-cost, high-volume Flash solution -- 60K x 16-bit words of Program Flash -- 2K x 16-bit words of Program RAM -- 8K x 16-bit words of Data Flash -- 4K x 16-bit words of Data RAM -- 2K x 16-bit words of Boot Flash * Off-chip memory expansion capabilities programmable for 0, 4, 8, or 12 wait states -- As much as 64K x 16 bits of Data memory -- As much as 64K x 16 bits of Program memory 1.1.3 * * * Peripheral Circuits for 56F807 Two Pulse Width Modulator modules each with six PWM outputs, three Current Sense inputs, and four Fault inputs, fault tolerant design with dead time insertion, supports both center- and edge-aligned modes Four 12-bit, Analog-to-Digital Converters (ADCs), which support four simultaneous conversions with quad, 4-pin multiplexed inputs; ADC and PWM modules can be synchronized Two Quadrature Decoders each with four inputs or two additional Quad Timers 56F807 Technical Data Technical Data, Rev. 15 4 Freescale Semiconductor 56F807 Description * * * * * * * * * * * Two dedicated General Purpose Quad Timers totaling six pins: Timer C with two pins and Timer D with four pins CAN 2.0 B Module with 2-pin port for transmit and receive Two Serial Communication Interfaces each with two pins (or four additional GPIO lines) Serial Peripheral Interface (SPI) with configurable 4-pin port (or four additional GPIO lines) Computer-Operating Properly (COP) Watchdog timer Two dedicated external interrupt pins 14 dedicated General Purpose I/O (GPIO) pins, 18 multiplexed GPIO pins External reset input pin for hardware reset External reset output pin for system reset JTAG/On-Chip Emulation (OnCETM) for unobtrusive, processor speed-independent debugging Software-programmable, Phase Locked Loop-based frequency synthesizer for the controller core clock 1.1.4 * * * * Energy Information Fabricated in high-density CMOS with 5V-tolerant, TTL-compatible digital inputs Uses a single 3.3V power supply On-chip regulators for digital and analog circuitry to lower cost and reduce noise Wait and Stop modes available 1.2 56F807 Description The 56F807 is a member of the 56800 core-based family of processors. It combines, on a single chip, the processing power of a DSP and the functionality of a microcontroller with a flexible set of peripherals to create an extremely cost-effective solution. Because of its low cost, configuration flexibility, and compact program code, the 56F807 is well-suited for many applications. The 56F807 includes many peripherals that are especially useful for applications such as motion control, smart appliances, steppers, encoders, tachometers, limit switches, power supply and control, automotive control, engine management, noise suppression, remote utility metering, industrial control for power, lighting, and automation. The 56800 core is based on a Harvard-style architecture consisting of three execution units operating in parallel, allowing as many as six operations per instruction cycle. The MCU-style programming model and optimized instruction set allow straightforward generation of efficient, compact DSP and control code. The instruction set is also highly efficient for C/C++ Compilers to enable rapid development of optimized control applications. The 56F807 supports program execution from either internal or external memories. Two data operands can be accessed from the on-chip Data RAM per instruction cycle. The 56F807 also provides two external dedicated interrupt lines and up to 32 General Purpose Input/Output (GPIO) lines, depending on peripheral configuration. The 56F807 controller includes 60K, 16-bit words of Program Flash and 8K words of Data Flash (each programmable through the JTAG port) with 2K words of Program RAM and 4K words of Data RAM. It also supports program execution from external memory. 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 5 A total of 2K words of Boot Flash is incorporated for easy customer-inclusion of field-programmable software routines that can be used to program the main Program and Data Flash memory areas. Both Program and Data Flash memories can be independently bulk erased or erased in page sizes of 256 words. The Boot Flash memory can also be either bulk or page erased. A key application-specific feature of the 56F807 is the inclusion of two Pulse Width Modulator (PWM) modules. These modules each incorporate three complementary, individually programmable PWM signal outputs (each module is also capable of supporting six independent PWM functions, for a total of 12 PWM outputs) to enhance motor control functionality. Complementary operation permits programmable dead time insertion, distortion correction via current sensing by software, and separate top and bottom output polarity control. The up-counter value is programmable to support a continuously variable PWM frequency. Edge- and center-aligned synchronous pulse width control (0% to 100% modulation) is supported. The device is capable of controlling most motor types: ACIM (AC Induction Motors), both BDC and BLDC (Brush and Brushless DC motors), SRM and VRM (Switched and Variable Reluctance Motors), and stepper motors. The PWMs incorporate fault protection and cycle-by-cycle current limiting with sufficient output drive capability to directly drive standard optoisolators. A "smoke-inhibit", write-once protection feature for key parameters is also included. A patented PWM waveform distortion correction circuit is also provided. Each PWM is double-buffered and includes interrupt controls to permit integral reload rates to be programmable from 1 to 16. The PWM modules provide a reference output to synchronize the analog-to-digital converters. The 56F807 incorporates two separate Quadrature Decoders capable of capturing all four transitions on the two-phase inputs, permitting generation of a number proportional to actual position. Speed computation capabilities accommodate both fast- and slow-moving shafts. An integrated watchdog timer in the Quadrature Decoder can be programmed with a time-out value to alarm when no shaft motion is detected. Each input is filtered to ensure only true transitions are recorded. This controller also provides a full set of standard programmable peripherals that include two Serial Communications Interfaces (SCI), one Serial Peripheral Interface (SPI), and four Quad Timers. Any of these interfaces can be used as General-Purpose Input/Outputs (GPIO) if that function is not required. A Controller Area Network interface (CAN Version 2.0 A/B-compliant), an internal interrupt controller, and 14 dedicated GPIO lines are also included on the 56F807. 1.3 State of the Art Development Environment * * Processor ExpertTM (PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use component-based software application creation with an expert knowledge system. The Code Warrior Integrated Development Environment is a sophisticated tool for code navigation, compiling, and debugging. A complete set of evaluation modules (EVMs) and development system cards will support concurrent engineering. Together, PE, Code Warrior and EVMs create a complete, scalable tools solution for easy, fast, and efficient development. 56F807 Technical Data Technical Data, Rev. 15 6 Freescale Semiconductor Product Documentation 1.4 Product Documentation The four documents listed in Table 1-1 are required for a complete description and proper design with the 56F807. Documentation is available from local Freescale distributors, Freescale Semiconductor sales offices, Freescale Literature Distribution Centers, or online at http://www.freescale.com. Table 1-1 56F807 Chip Documentation Topic 56800E Family Manual DSP56F801/803/805/807 User's Manual 56F807 Technical Data Sheet 56F807 Errata Description Detailed description of the 56800 family architecture, and 16-bit core processor and the instruction set Detailed description of memory, peripherals, and interfaces of the 56F801, 56F803, 56F805, and 56F807 Electrical and timing specifications, pin descriptions, and package descriptions (this document) Details any chip issues that might be present Order Number 56800EFM DSP56F801-7UM DSP56F807 56F807E 1.5 Data Sheet Conventions This data sheet uses the following conventions: OVERBAR This is used to indicate a signal that is active when pulled low. For example, the RESET pin is active when low. A high true (active high) signal is high or a low true (active low) signal is low. A high true (active high) signal is low or a low true (active low) signal is high. Signal/Symbol PIN PIN PIN PIN Logic State True False True False Signal State Asserted Deasserted Asserted Deasserted Voltage1 VIL/VOL VIH/VOH VIH/VOH VIL/VOL "asserted" "deasserted" Examples: 1. Values for VIL, VOL, VIH, and VOH are defined by individual product specifications. 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 7 Part 2 Signal/Connection Descriptions 2.1 Introduction The input and output signals of the 56F807 are organized into functional groups, as shown in Table 2-1 and as illustrated in Figure 2-1. In Table 2-2 through Table 2-19, each table row describes the signal or signals present on a pin. Table 2-1 Functional Group Pin Allocations Functional Group Power (VDD or VDDA) Ground (VSS or VSSA) Supply Capacitors & VPP PLL and Clock Address Bus1 Data Bus Bus Control Interrupt and Program Control Dedicated General Purpose Input/Output Pulse Width Modulator (PWM) Ports Serial Peripheral Interface (SPI) Port1 Quadrature Decoder Ports2 Serial Communications Interface (SCI) Ports1 CAN Port Analog to Digital Converter (ADC) Ports Quad Timer Module Ports JTAG/On-Chip Emulation (OnCE) 1. Alternately, GPIO pins 2. Alternately, Quad Timer pins Number of Pins 11 13 4 3 16 16 4 5 14 26 4 8 4 2 20 6 6 Detailed Description Table 2-2 Table 2-3 Table 2-4 Table 2-5 Table 2-6 Table 2-7 Table 2-8 Table 2-9 Table 2-10 Table 2-11 Table 2-12 Table 2-13 Table 2-15 Table 2-16 Table 2-17 Table 2-18 Table 2-19 56F807 Technical Data Technical Data, Rev. 15 8 Freescale Semiconductor Introduction Power Port Ground Port Power Port Ground Port VDD VSS VDDA VSSA 8 10* 3 3 8 6 GPIOB0-7 GPIOD0-5 Dedicated GPIO 6 3 PWMA0-5 ISA0-2 FAULTA0-3 PWMA Port Other Supply Ports PLL and Clock VCAPC VPP 2 2 4 EXTAL XTAL CLKO 6 1 1 1 1 6 2 8 1 1 1 3 PWMB0-5 ISB0-2 FAULTB0-3 PWMB Port 56F807 4 SCLK (GPIOE4) MOSI (GPIOE5) MISO (GPIOE6) SS (GPIOE7) SPI Port or GPIO A0-A5 External Address Bus or GPIO A6-7 (GPIOE2-E3) A8-15 (GPIOA0-A7) External Data Bus D0-D15 16 1 1 TXD0 (GPIOE0) RXD0 (GPIOE1) SCI0 Port or GPIO PS External Bus Control DS RD WR 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 4 TC0-1 TD0-3 Quad Timers C&D 1 1 MSCAN_RX MSCAN_TX CAN 2 8 ANA0-7 VREF ANB0-7 ADCA Port ADCB Port 1 1 TXD1 (GPIOD6) RXD1 (GPIOD7) SCI1 Port or GPI0 PHASEA0 (TA0) Quadrature Decoder or Quad Timer A PHASEB0 (TA1) INDEX0 (TA2) HOME0 (TA3) PHASEA1 (TB0) Quadrature Decoder1 or Quad Timer B PHASEB1 (TB1) INDEX1 (TB2) HOME1 (TB3) TCK TMS JTAG/OnCETM Port TDI TDO TRST DE IRQA IRQB RESET RSTO EXTBOOT Interrupt/ Program Control *includes TCS pin which is reserved for factory use and is tied to VSS Figure 2-1 56F807 Signals Identified by Functional Group1 1. Alternate pin functionality is shown in parenthesis. 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 9 2.2 Power and Ground Signals Table 2-2 Power Inputs No. of Pins 8 3 Signal Name VDD VDDA Signal Description Power--These pins provide power to the internal structures of the chip, and should all be attached to VDD. Analog Power--These pins is a dedicated power pin for the analog portion of the chip and should be connected to a low noise 3.3V supply. Table 2-3 Grounds No. of Pins 9 3 1 Signal Name VSS VSSA TCS Signal Description GND--These pins provide grounding for the internal structures of the chip and should all be attached to VSS. Analog Ground--This pin supplies an analog ground. TCS--This Schmitt pin is reserved for factory use and must be tied to VSS for normal use. In block diagrams, this pin is considered an additional VSS. Table 2-4 Supply Capacitors and VPP No. of Pins 2 Signal Name VCAPC Signal Type Supply State During Reset Supply Signal Description VCAPC--Connect each pin to a 2.2uF or greater bypass capacitor in order to bypass the core logic voltage regulator (required for proper chip operation). For more information, please refer to Section 5.2 VPP--This pin should be left unconnected as an open circuit for normal functionality. 2 VPP Input Input 56F807 Technical Data Technical Data, Rev. 15 10 Freescale Semiconductor Clock and Phase Locked Loop Signals 2.3 Clock and Phase Locked Loop Signals Table 2-5 PLL and Clock No. of Pins 1 Signal Name EXTAL Signal Type Input State During Reset Input Signal Description External Crystal Oscillator Input--This input should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.4. Crystal Oscillator Output--This output should be connected to an 8MHz external crystal or ceramic resonator. For more information, please refer to Section 3.4. This pin can also be connected to an external clock source. For more information, please refer to Section 3.4.2. 1 CLKO Output Chip-driven Clock Output--This pin outputs a buffered clock signal. By programming the CLKOSEL[4:0] bits in the CLKO Select Register (CLKOSR), the user can select between outputting a version of the signal applied to XTAL and a version of the device's master clock at the output of the PLL. The clock frequency on this pin can also be disabled by programming the CLKOSEL[4:0] bits in CLKOSR. 1 XTAL Input/ Output Chip-driven 2.4 Address, Data, and Bus Control Signals Table 2-6 Address Bus Signals No. of Pins 6 2 Signal Name A0-A5 A6-A7 Signal Type Output Output State During Reset Tri-stated Tri-stated Signal Description Address Bus--A0-A5 specify the address for external Program or Data memory accesses. Address Bus--A6-A7 specify the address for external Program or Data memory accesses. Port E GPIO--These two General Purpose I/O (GPIO) pins can individually be programmed as input or output pins. After reset, the default state is Address Bus. 8 A8-A15 Output Tri-stated Address Bus--A8-A15 specify the address for external Program or Data memory accesses. Port A GPIO--These eight General Purpose I/O (GPIO) pins can be individually programmed as input or output pins. After reset, the default state is Address Bus. GPIOE2GPIOE3 Input/O utput Input GPIOA0GPIOA7 Input/O utput Input 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 11 Table 2-7 Data Bus Signals No. of Pins 16 Signal Name D0-D15 Signal Type Input/O utput State During Reset Tri-stated Signal Description Data Bus-- D0-D15 specify the data for external program or data memory accesses. D0-D15 are tri-stated when the external bus is inactive. Internal pullups may be active. Table 2-8 Bus Control Signals No. of Pins 1 1 1 Signal Name PS DS WR Signal Type Output Output Output State During Reset Tri-stated Tri-stated Tri-stated Signal Description Program Memory Select--PS is asserted low for external program memory access. Data Memory Select--DS is asserted low for external data memory access. Write Enable--WR is asserted during external memory write cycles. When WR is asserted low, pins D0-D15 become outputs and the device puts data on the bus. When WR is deasserted high, the external data is latched inside the external device. When WR is asserted, it qualifies the A0-A15, PS, and DS pins. WR can be connected directly to the WE pin of a Static RAM. Read Enable--RD is asserted during external memory read cycles. When RD is asserted low, pins D0-D15 become inputs and an external device is enabled onto the device's data bus. When RD is deasserted high, the external data is latched inside the device. When RD is asserted, it qualifies the A0-A15, PS, and DS pins. RD can be connected directly to the OE pin of a Static RAM or ROM. 1 RD Output Tri-stated 2.5 Interrupt and Program Control Signals Table 2-9 Interrupt and Program Control Signals No. of Pins 1 Signal Name IRQA Signal Type Input (Schmitt) State During Reset Input Signal Description External Interrupt Request A--The IRQA input is a synchronized external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. External Interrupt Request B--The IRQB input is an external interrupt request that indicates that an external device is requesting service. It can be programmed to be level-sensitive or negative-edge-triggered. 1 IRQB Input (Schmitt) Input 56F807 Technical Data Technical Data, Rev. 15 12 Freescale Semiconductor GPIO Signals Table 2-9 Interrupt and Program Control Signals (Continued) No. of Pins 1 1 Signal Name RSTO RESET Signal Type Output Input (Schmitt) State During Reset Output Input Signal Description Reset Output--This output reflects the internal reset state of the chip. Reset--This input is a direct hardware reset on the processor. When RESET is asserted low, the device is initialized and placed in the Reset state. A Schmitt trigger input is used for noise immunity. When the RESET pin is deasserted, the initial chip operating mode is latched from the EXTBOOT pin. The internal reset signal will be deasserted synchronous with the internal clocks, after a fixed number of internal clocks. To ensure complete hardware reset, RESET and TRST should be asserted together. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. 1 EXTBOOT Input (Schmitt) Input External Boot--This input is tied to VDD to force device to boot from off-chip memory. Otherwise, it is tied to VSS. 2.6 GPIO Signals Table 2-10 Dedicated General Purpose Input/Output (GPIO) Signals No. of Pins 8 Signal Name GPIOB0GPIOB7 Signal Type Input or Output State During Reset Input Signal Description Port B GPIO--These eight pins are dedicated General Purpose I/O (GPIO) pins that can individually be programmed as input or output pins. After reset, the default state is GPIO input. 6 GPIOD0GPIOD5 Input or Output Input Port D GPIO--These six pins are dedicated GPIO pins that can individually be programmed as an input or output pins. After reset, the default state is GPIO input. 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 13 2.7 Pulse Width Modulator (PWM) Signals Table 2-11 Pulse Width Modulator (PWMA and PWMB) Signals No. of Pins 6 3 Signal Name PWMA0-5 ISA0-2 Signal Type Output Input (Schmitt) State During Reset Tri- stated Input Signal Description PWMA0-5-- Six PWMA output pins. ISA0-2-- These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMA. FAULTA0-3-- These Fault input pins are used for disabling selected PWMA outputs in cases where fault conditions originate off-chip. PWMB0-5-- Six PWMB output pins. ISB0-2-- These three input current status pins are used for top/bottom pulse width correction in complementary channel operation for PWMB. FAULTB0-3-- These four Fault input pins are used for disabling selected PWMB outputs in cases where fault conditions originate off-chip. 4 FAULTA0-3 Input (Schmitt) Input 6 3 PWMB0-5 ISB0-2 Output Input (Schmitt) Tri- stated Input 4 FAULTB0-3 Input (Schmitt) Input 56F807 Technical Data Technical Data, Rev. 15 14 Freescale Semiconductor Serial Peripheral Interface (SPI) Signals 2.8 Serial Peripheral Interface (SPI) Signals Table 2-12 Serial Peripheral Interface (SPI) Signals No. of Pins 1 Signal Name MISO Signal Type Input/ Output State During Reset Input Signal Description SPI Master In/Slave Out (MISO)--This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is MISO. 1 MOSI Input/ Output Input SPI Master Out/Slave In (MOSI)--This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is MOSI. 1 SCLK Input/Outp ut Input SPI Serial Clock--In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCLK. 1 SS Input Input SPI Slave Select--In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SS. GPIOE6 Input/Outp ut Input GPIOE5 Input/Outp ut Input GPIOE4 Input/Outp ut Input GPIOE7 Input/Outp ut Input 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 15 2.9 Quadrature Decoder Signals Table 2-13 Quadrature Decoder (Quad Dec0 and Quad Dec1) Signals No. of Pins 1 Signal Name PHASEA0 TA0 1 PHASEB0 TA1 1 INDEX0 TA2 1 HOME0 TA3 1 PHASEA1 TB0 1 PHASEB1 TB1 1 INDEX1 TB2 1 HOME1 TB3 Signal Type Input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input/Output Input Input/Output State During Reset Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Input Signal Description Phase A--Quadrature Decoder #0 PHASEA input TA0--Timer A Channel 0 Phase B--Quadrature Decoder #0 PHASEB input TA1--Timer A Channel 1 Index--Quadrature Decoder #0 INDEX input TA2--Timer A Channel 2 Home--Quadrature Decoder #0 HOME input TA3--Timer A Channel 3 Phase A--Quadrature Decoder #1 PHASEA input TB0--Timer B Channel 0 Phase B--Quadrature Decoder #1 PHASEB input TB1--Timer B Channel 1 Index--Quadrature Decoder #1 INDEX input TB2--Timer B Channel 2 Home--Quadrature Decoder #1 HOME input TB3--Timer B Channel 3 56F807 Technical Data Technical Data, Rev. 15 16 Freescale Semiconductor Serial Communications Interface (SCI) Signals 2.10 Serial Communications Interface (SCI) Signals Table 2-14 Serial Peripheral Interface (SPI) Signals No. of Pins 1 Signal Name MISO Signal Type Input/ Output State During Reset Input Signal Description SPI Master In/Slave Out (MISO)--This serial data pin is an input to a master device and an output from a slave device. The MISO line of a slave device is placed in the high-impedance state if the slave device is not selected. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is MISO. 1 MOSI Input/ Output Input SPI Master Out/Slave In (MOSI)--This serial data pin is an output from a master device and an input to a slave device. The master device places data on the MOSI line a half-cycle before the clock edge that the slave device uses to latch the data. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is MOSI. 1 SCLK Input/Outp ut Input SPI Serial Clock--In master mode, this pin serves as an output, clocking slaved listeners. In slave mode, this pin serves as the data clock input. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCLK. 1 SS Input Input SPI Slave Select--In master mode, this pin is used to arbitrate multiple masters. In slave mode, this pin is used to select the slave. Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SS. GPIOE6 Input/Outp ut Input GPIOE5 Input/Outp ut Input GPIOE4 Input/Outp ut Input GPIOE7 Input/Outp ut Input 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 17 Table 2-15 Serial Communications Interface (SCI0 and SCI1) Signals No. of Pins 1 Signal Name TXD0 GPIOE0 Signal Type Output Input/Outp ut State During Reset Input Input Signal Description Transmit Data (TXD0)--transmit data output Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI output. 1 RXD0 GPIOE1 Input Input/Outp ut Input Input Receive Data (RXD0)-- receive data input Port E GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI input. 1 TXD1 GPIOD6 Output Input/Outp ut Input Input Transmit Data (TXD1)--transmit data output Port D GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI output. 1 RXD1 GPIOD7 Input Input/Outp ut Input Input Receive Data (RXD1)-- receive data input Port D GPIO--This pin is a General Purpose I/O (GPIO) pin that can individually be programmed as input or output pin. After reset, the default state is SCI input. 2.11 CAN Signals Table 2-16 CAN Module Signals No. of Pins 1 1 Signal Name MSCAN_ RX MSCAN_ TX Signal Type Input (Schmitt) Output State During Reset Input Output Signal Description MSCAN Receive Data--MSCAN input. This pin has an internal pull-up resistor. MSCAN Transmit Data--MSCAN output. CAN output is open-drain output and pull-up resistor is needed. 56F807 Technical Data Technical Data, Rev. 15 18 Freescale Semiconductor Analog-to-Digital Converter (ADC) Signals 2.12 Analog-to-Digital Converter (ADC) Signals Table 2-17 Analog to Digital Converter Signals No. of Pins 4 4 2 4 4 Signal Name ANA0-3 ANA4-7 VREF ANB0-3 ANB4-7 Signal Type Input Input Input Input Input State During Reset Input Input Input Input Input Signal Description ANA0-3--Analog inputs to ADCA channel 1 ANA4-7--Analog inputs to ADCA channel 2 VREF--Analog reference voltage for ADC. Must be set to VDDA-0.3V for optimal performance. ANB0-3--Analog inputs to ADCB, channel 1 ANB4-7--Analog inputs to ADCB, channel 2 2.13 Quad Timer Module Signals Table 2-18 Quad Timer Module Signals No. of Pins 2 4 Signal Name TC0-1 TD0-3 Signal Type Input/Output Input/Output State During Reset Input Input Signal Description TC0-1--Timer C Channels 0 and 1 TD0-3--Timer D Channels 0, 1, 2, and 3 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 19 2.14 JTAG/OnCE Table 2-19 JTAG/On-Chip Emulation (OnCE) Signals No. of Pins 1 Signal Name TCK Signal Type Input (Schmitt) Input (Schmitt) State During Reset Input, pulled low internally Signal Description Test Clock Input--This input pin provides a gated clock to synchronize the test logic and shift serial data to the JTAG/OnCE port. The pin is connected internally to a pull-down resistor. 1 TMS Input, pulled Test Mode Select Input--This input pin is used to sequence the JTAG high internally TAP controller's state machine. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Note: Always tie the TMS pin to VDD through a 2.2K resistor. 1 TDI Input (Schmitt) Output Input, pulled Test Data Input--This input pin provides a serial input data stream to high internally the JTAG/OnCE port. It is sampled on the rising edge of TCK and has an on-chip pull-up resistor. Tri-stated Test Data Output--This tri-statable output pin provides a serial output data stream from the JTAG/OnCE port. It is driven in the Shift-IR and Shift-DR controller states, and changes on the falling edge of TCK. 1 TDO 1 TRST Input (Schmitt) Input, pulled Test Reset--As an input, a low signal on this pin provides a reset signal high internally to the JTAG TAP controller. To ensure complete hardware reset, TRST should be asserted at power-up and whenever RESET is asserted. The only exception occurs in a debugging environment when a hardware device reset is required and it is necessary not to reset the OnCE/JTAG module. In this case, assert RESET, but do not assert TRST. Note: For normal operation, connect TRST directly to VSS. If the design is to be used in a debugging environment, TRST may be tied to VSS through a 1K resistor. 1 DE Output Output Debug Event--DE provides a low pulse on recognized debug events. Part 3 Specifications 3.1 General Characteristics The 56F807 is fabricated in high-density CMOS with 5V-tolerant TTL-compatible digital inputs. The term "5V-tolerant" refers to the capability of an I/O pin, built on a 3.3V compatible process technology, to withstand a voltage up to 5.5V without damaging the device. Many systems have a mixture of devices designed for 3.3V and 5V power supplies. In such systems, a bus may carry both 3.3V and 5V-compatible I/O voltage levels (a standard 3.3V I/O is designed to receive a maximum voltage of 3.3V 10% during normal operation without causing damage). This 5V-tolerant capability therefore offers the power savings of 3.3V I/O levels while being able to receive 5V levels without being damaged. Absolute maximum ratings given in Table 3-1 are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond these ratings may affect device reliability or cause permanent 56F807 Technical Data Technical Data, Rev. 15 20 Freescale Semiconductor General Characteristics damage to the device. The 56F807 DC/AC electrical specifications are preliminary and are from design simulations. These specifications may not be fully tested or guaranteed at this early stage of the product life cycle. Finalized specifications will be published after complete characterization and device qualifications have been completed. CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Table 3-1 Absolute Maximum Ratings Characteristic Supply voltage All other input voltages, excluding Analog inputs Voltage difference VDD to VDDA Voltage difference VSS to VSSA Analog inputs, ANA0-7 and VREF Analog inputs EXTAL and XTAL Current drain per pin excluding VDD, VSS, PWM outputs, TCS, VPP, VDDA, VSSA Symbol VDD VIN VDD VSS VIN VIN I Min VSS - 0.3 VSS - 0.3 - 0.3 - 0.3 VSSA- 0.3 VSSA- 0.3 -- Max VSS + 4.0 VSS + 5.5V 0.3 0.3 VDDA+ 0.3 VSSA+ 3.0 10 Unit V V V V V V mA Table 3-2 Recommended Operating Conditions Characteristic Supply voltage, digital Supply Voltage, analog Voltage difference VDD to VDDA Symbol VDD VDDA VDD Min 3.0 3.0 -0.1 Typ 3.3 3.3 Max 3.6 3.6 0.1 Unit V V V 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 21 Table 3-2 Recommended Operating Conditions Characteristic Voltage difference VSS to VSSA ADC reference voltage Ambient operating temperature Symbol VSS VREF TA Min -0.1 2.7 -40 Typ - - Max 0.1 VDDA 85 Unit V V C Table 3-3 Thermal Characteristics6 Value Characteristic Comments Symbol 160-pin LQFP 38.5 160 MBGA 63.4 Unit Notes Junction to ambient Natural convection Junction to ambient (@1m/sec) Junction to ambient Natural convection Junction to ambient (@1m/sec) Four layer board (2s2p) Four layer board (2s2p) RJA RJMA RJMA (2s2p) RJMA RJC JT P I/O PD PDMAX C/W 2 35.4 33 60.3 49.9 C/W C/W 2 1,2 31.5 46.8 C/W 1,2 Junction to case Junction to center of case I/O pin power dissipation Power dissipation Junction to center of case 8.6 0.8 8.1 0.6 C/W C/W W W W 3 4, 5 User Determined P D = (IDD x VDD + P I/O) (TJ - TA) /RJA 7 Notes: 1. 2. Theta-JA determined on 2s2p test boards is frequently lower than would be observed in an application. Determined on 2s2p thermal test board. Junction to ambient thermal resistance, Theta-JA (RJA) was simulated to be equivalent to the JEDEC specification JESD51-2 in a horizontal configuration in natural convection. Theta-JA was also simulated on a thermal test board with two internal planes (2s2p where "s" is the number of signal layers and "p" is the number of planes) per JESD51-6 and JESD51-7. The correct name for Theta-JA for forced convection or with the non-single layer boards is Theta-JMA. Junction to case thermal resistance, Theta-JC (RJC ), was simulated to be equivalent to the measured values using the cold plate technique with the cold plate temperature used as the "case" temperature. The basic cold plate measurement technique is described by MIL-STD 883D, Method 1012.1. This is the correct thermal metric to use to calculate thermal performance when the package is being used with a heat sink. 3. 56F807 Technical Data Technical Data, Rev. 15 22 Freescale Semiconductor DC Electrical Characteristics 4. Thermal Characterization Parameter, Psi-JT (JT ), is the "resistance" from junction to reference point thermocouple on top center of case as defined in JESD51-2. JT is a useful value to use to estimate junction temperature in steady state customer environments. Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. See Section 5.1 from more details on thermal design considerations. TJ = Junction Temperature TA = Ambient Temperature 5. 6. 7. 3.2 DC Electrical Characteristics Table 3-4 DC Electrical Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fop = 80MHz Characteristic Input high voltage (XTAL/EXTAL) Input low voltage (XTAL/EXTAL) Input high voltage (Schmitt trigger inputs)1 Input low voltage (Schmitt trigger inputs)1 Input high voltage (all other digital inputs) Input low voltage (all other digital inputs) Input current high (pullup/pulldown resistors disabled, VIN=VDD) Input current low (pullup/pulldown resistors disabled, VIN=VSS) Input current high (with pullup resistor, VIN=VDD) Input current low (with pullup resistor, VIN=VSS) Input current high (with pulldown resistor, VIN=VDD) Input current low (with pulldown resistor, VIN=VSS) Nominal pullup or pulldown resistor value Output tri-state current low Output tri-state current high Input current high (analog inputs, VIN=VDDA)2 Input current low (analog inputs, VIN=VSSA)3 Output High Voltage (at IOH) Symbol VIHC VILC VIHS VILS VIH VIL IIH IIL IIHPU IILPU IIHPD IILPD RPU, RPD IOZL IOZH IIHA IILA VOH -10 -10 -15 -15 VDD - 0.7 Min 2.25 0 2.2 -0.3 2.0 -0.3 -1 -1 -1 -210 20 -1 Typ -- -- -- -- -- -- -- -- -- -- -- -- 30 -- -- -- -- -- 10 10 15 15 -- Max 2.75 0.5 5.5 0.8 5.5 0.8 1 1 1 -50 180 1 Unit V V V V V V A A A A A A K A A A A V 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 23 Table 3-4 DC Electrical Characteristics (Continued) Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fop = 80MHz Characteristic Output Low Voltage (at IOL) Output source current Output source current PWM pin output source current3 PWM pin output sink current4 Input capacitance Output capacitance VDD supply current Run 6 Wait7 Stop Low Voltage Interrupt, external power supply8 Low Voltage Interrupt, internal power supply9 Power on Reset10 VEIO VEIC VPOR Symbol VOL IOH IOL IOHP IOLP CIN COUT IDDT5 -- -- -- 2.4 2.0 -- 195 170 115 2.7 2.2 1.7 220 200 145 3.0 2.4 2.0 mA mA mA V V V Min -- 4 4 10 16 -- -- Typ -- -- -- -- -- 8 12 Max 0.4 -- -- -- -- -- -- Unit V mA mA mA mA pF pF 1. Schmitt Trigger inputs are: EXTBOOT, IRQA, IRQB, RESET, TCS, ISA0-2, FAULTA0-3, ISB0-2, FAULTB0-3, TCK, TRST, TMS, TDI, and MSCAN_RX 2. Analog inputs are: ANA[0:7], XTAL and EXTAL. Specification assumes ADC is not sampling. 3. PWM pin output source current measured with 50% duty cycle. 4. PWM pin output sink current measured with 50% duty cycle. 5. IDDT = IDD + IDDA (Total supply current for VDD + VDDA) 6. Run (operating) IDD measured using 8MHz clock source. All inputs 0.2V from rail; outputs unloaded. All ports configured as inputs; measured with all modules enabled. 7. Wait IDD measured using external square wave clock source (fosc = 8MHz) into XTAL; all inputs 0.2V from rail; no DC loads; less than 50pF on all outputs. CL = 20pF on EXTAL; all ports configured as inputs; EXTAL capacitance linearly affects wait IDD; measured with PLL enabled. 8. This low voltage interrupt monitors the VDDA external power supply. VDDA is generally connected to the same potential as VDD via separate traces. If VDDA drops below VEIO, an interrupt is generated. Functionality of the device is guaranteed under transient conditions when VDDA>VEIO (between the minimum specified VDD and the point when the VEIO interrupt is generated). 9. This low voltage interrupt monitors the internally regulated core power supply. If the output from the internal voltage is regulator drops below VEIC, an interrupt is generated. Since the core logic supply is internally regulated, this interrupt will not be generated unless the external power supply drops below the minimum specified value (3.0V). 10. Power-on reset occurs whenever the internally regulated 2.5V digital supply drops below 1.5V typical. While power is ramping up, this signal remains active as long as the internal 2.5V is below 1.5V typical, no matter how long the ramp-up rate is. The internally regulated voltage is typically 100mV less than VDD during ramp-up until 2.5V is reached, at which time it self-regulates. 56F807 Technical Data Technical Data, Rev. 15 24 Freescale Semiconductor AC Electrical Characteristics 250 IDD Digital IDD Analog IDD Total 200 150 IDD (mA) 100 50 0 10 20 30 40 50 60 70 80 Freq. (MHz) Figure 3-1 Maximum Run IDD vs. Frequency (see Note 6. in Table 3-14) 3.3 AC Electrical Characteristics Timing waveforms in Section 3.3 are tested using the VIL and VIH levels specified in the DC Characteristics table. In Figure 3-2 the levels of VIH and VIL for an input signal are shown. VIH Input Signal Midpoint1 Fall Time Note: The midpoint is VIL + (VIH - VIL)/2. Low High 90% 50% 10% VIL Rise Time Figure 3-2 Input Signal Measurement References Figure 3-3 shows the definitions of the following signal states: * * * * Active state, when a bus or signal is driven, and enters a low impedance state Tri-stated, when a bus or signal is placed in a high impedance state Data Valid state, when a signal level has reached VOL or VOH Data Invalid state, when a signal level is in transition between VOL and VOH 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 25 Data1 Valid Data1 Data Invalid State Data Active Data2 Valid Data2 Data Tri-stated Data3 Valid Data3 Data Active Figure 3-3 Signal States Table 3-5 Flash Memory Truth Table Mode Standby Read Word Program Page Erase Mass Erase XE1 L H H H H YE2 L H H L L SE3 L H L L L OE4 L H L L L PROG5 L L H L L ERASE6 L L L H H MAS17 L L L L H NVSTR8 L L H H H 1. X address enable, all rows are disabled when XE=0 2. Y address enable, YMUX is disabled when YE=0 3. Sense amplifier enable 4. Output enable, tri-state Flash data out bus when OE=0 5. Defines program cycle 6. Defines erase cycle 7. Defines mass erase cycle, erase whole block 8. Defines non-volatile store cycle Table 3-6 IFREN Truth Table Mode Read Word program Page erase Mass erase IFREN=1 Read information block Program information block Erase information block Erase both block IFREN=0 Read main memory block Program main memory block Erase main memory block Erase main memory block 56F807 Technical Data Technical Data, Rev. 15 26 Freescale Semiconductor AC Electrical Characteristics Table 3-7 Flash Timing Parameters Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6V, TA = -40 to +85C, CL 50pF Characteristic Program time Erase time Mass erase time Endurance1 Data Retention1 Symbol Min 20 20 100 10,000 10 Typ - - - 20,000 30 Max - - - - - Unit us ms ms cycles years Figure Figure 3-4 Figure 3-5 Figure 3-6 Tprog* Terase* Tme* ECYC DRET The following parameters should only be used in the Manual Word Programming Mode PROG/ERASE to NVSTR set up time NVSTR hold time NVSTR hold time (mass erase) NVSTR to program set up time Recovery time Tnvs* - 5 - us Figure 3-4, Figure 3-5, Figure 3-6 Figure 3-4, Figure 3-5 Figure 3-6 Figure 3-4 Figure 3-4, Figure 3-5, Figure 3-6 Figure 3-4 Tnvh* Tnvh1* Tpgs* Trcv* - - - - 5 100 10 1 - - - - us us us us Cumulative program HV period2 Program hold time3 Address/data set up time3 Address/data hold time3 Thv Tpgh Tads Tadh - 3 - ms - - - - - - - - - Figure 3-4 Figure 3-4 Figure 3-4 1. One cycle is equal to an erase program and read. 2. Thv is the cumulative high voltage programming time to the same row before next erase. The same address cannot be programmed twice before next erase. 3. Parameters are guaranteed by design in smart programming mode and must be one cycle or greater. *The Flash interface unit provides registers for the control of these parameters. 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 27 IFREN XADR XE Tadh YADR YE DIN Tads PROG Tnvs NVSTR Tpgs Thv Tnvh Trcv Tprog Tpgh Figure 3-4 Flash Program Cycle IFREN XADR XE YE=SE=OE=MAS1=0 ERASE Tnvs NVSTR Tnvh Terase Trcv Figure 3-5 Flash Erase Cycle 56F807 Technical Data Technical Data, Rev. 15 28 Freescale Semiconductor External Clock Operation IFREN XADR XE MAS1 YE=SE=OE=0 ERASE Tnvs NVSTR Tnvh1 Tme Trcv Figure 3-6 Flash Mass Erase Cycle 3.4 External Clock Operation The 56F807 system clock can be derived from an external crystal or an external system clock signal. To generate a reference frequency using the internal oscillator, a reference crystal must be connected between the EXTAL and XTAL pins. 3.4.1 Crystal Oscillator The internal oscillator is also designed to interface with a parallel-resonant crystal resonator in the frequency range specified for the external crystal in Table 3-9. In Figure 3-7 a recommended crystal oscillator circuit is shown. Follow the crystal supplier's recommendations when selecting a crystal, since crystal parameters determine the component values required to provide maximum stability and reliable start-up. The crystal and associated components should be mounted as close as possible to the EXTAL and XTAL pins to minimize output distortion and start-up stabilization time. The internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-8 no external load capacitors should be used. The 56F80x components internally are modeled as a parallel resonant oscillator circuit to provide a capacitive load on each of the oscillator pins (XTAL and EXTAL) of 10pF to 13pF over temperature and process variations. Using a typical value of internal capacitance on these pins of 12pF and a value of 3pF 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 29 as a typical circuit board trace capacitance the parallel load capacitance presented to the crystal is 9pF as determined by the following equation: CL1 * CL2 CL = CL1 + CL2 + Cs = 12 + 12 12 * 12 + 3 = 6 + 3 = 9pF This is the value load capacitance that should be used when selecting a crystal and determining the actual frequency of operation of the crystal oscillator circuit. Recommended External Crystal Parameters: Rz = 1 to 3 M fc = 8MHz (optimized for 8MHz) EXTAL XTAL Rz fc Figure 3-7 Connecting to a Crystal Oscillator 3.4.2 Ceramic Resonator It is also possible to drive the internal oscillator with a ceramic resonator, assuming the overall system design can tolerate the reduced signal integrity. In Figure 3-8, a typical ceramic resonator circuit is shown. Refer to supplier's recommendations when selecting a ceramic resonator and associated components. The resonator and components should be mounted as close as possible to the EXTAL and XTAL pins. The internal 56F80x oscillator circuitry is designed to have no external load capacitors present. As shown in Figure 3-7 no external load capacitors should be used. EXTAL XTAL Rz fc Recommended Ceramic Resonator Parameters: Rz = 1 to 3 M fc = 8MHz (optimized for 8MHz) Figure 3-8 Connecting a Ceramic Resonator Note: Freescale recommends only two terminal ceramic resonators vs. three terminal resonators (which contain an internal bypass capacitor to ground). 56F807 Technical Data Technical Data, Rev. 15 30 Freescale Semiconductor External Clock Operation 3.4.3 External Clock Source The recommended method of connecting an external clock is given in Figure 3-9. The external clock source is connected to XTAL and the EXTAL pin is grounded. 56F807 XTAL EXTAL External Clock VSS Figure 3-9 Connecting an External Clock Signal Table 3-8 External Clock Operation Timing Requirements5 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C Characteristic Frequency of operation (external clock driver)1 Clock Pulse Width2, 3 Symbol fosc tPW Min 0 6.25 Typ -- -- Max 80 -- Unit MHz ns 1. See Figure 3-9 for details on using the recommended connection of an external clock driver. 2. The high or low pulse width must be no smaller than 6.25ns or the chip will not function. 3. Parameters listed are guaranteed by design. VIH External Clock 90% 50% 10% 90% 50% 10% tPW tPW VIL Note: The midpoint is VIL + (VIH - VIL)/2. Figure 3-10 External Clock Timing 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 31 3.4.4 Phase Locked Loop Timing Table 3-9 PLL Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C Characteristic Symbol fosc fout/2 tplls tplls Min 4 40 -- -- Typ 8 -- 1 100 Max 10 110 10 200 Unit MHz MHz ms ms External reference crystal frequency for the PLL1 PLL output frequency2 PLL stabilization time3 0o to +85oC PLL stabilization time3 -40o to 0oC 1. An externally supplied reference clock should be as free as possible from any phase jitter for the PLL to work correctly. The PLL is optimized for 8MHz input crystal.2. 2. ZCLK may not exceed 80MHz. For additional information on ZCLK and fout/2, please refer to the OCCS chapter in the User Manual. ZCLK = fop 3. This is the minimum time required after the PLL set-up is changed to ensure reliable operation. 56F807 Technical Data Technical Data, Rev. 15 32 Freescale Semiconductor External Bus Asynchronous Timing 3.5 External Bus Asynchronous Timing Table 3-10 External Bus Asynchronous Timing1,2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fop = 80MHz Characteristic Address Valid to WR Asserted WR Width Asserted Wait states = 0 Wait states > 0 WR Asserted to D0-D15 Out Valid Data Out Hold Time from WR Deasserted Data Out Set Up Time to WR Deasserted Wait states = 0 Wait states > 0 RD Deasserted to Address Not Valid Address Valid to RD Deasserted Wait states = 0 Wait states > 0 Input Data Hold to RD Deasserted RD Assertion Width Wait states = 0 Wait states > 0 Address Valid to Input Data Valid Wait states = 0 Wait states > 0 Address Valid to RD Asserted RD Asserted to Input Data Valid Wait states = 0 Wait states > 0 WR Deasserted to RD Asserted RD Deasserted to RD Asserted WR Deasserted to WR Asserted RD Deasserted to WR Asserted Symbol tAWR tWR 7.5 (T*WS)+7.5 tWRD tDOH tDOS 2.2 (T*WS)+6.4 tRDA tARDD 18.7 (T*WS) + 18.7 tDRD tRD 19 (T*WS)+19 tAD -- -- tARDA tRDD -- -- tWRRD tRDRD tWRWR tRDWR 6.8 0 14.1 12.8 2.4 (T*WS) + 2.4 -- -- -- -- ns ns ns ns ns ns -4.4 1 (T*WS)+1 -- ns ns ns -- -- ns ns 0 -- 0 -- -- -- -- ns ns ns ns ns ns -- 4.8 -- -- T + 4.2 -- ns ns ns ns Min 6.5 Max -- Unit ns 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 33 1. Timing is both wait state and frequency dependent. In the formulas listed, WS = the number of wait states and T = Clock Period. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. To calculate the required access time for an external memory for any frequency < 80MHz, use this formula: Top = Clock period @ desired operating frequency WS = Number of wait states Memory Access Time = (Top*WS) + (Top- 11.5) A0-A15, PS, DS (See Note) tARDA tARDD tRDA tRDRD RD tAWR tWRWR tWR tWRRD tRD tRDWR WR tWRD tDOS tAD tDOH tRDD tDRD D0-D15 Data Out Data In Note: During read-modify-write instructions and internal instructions, the address lines do not change state. Figure 3-11 External Bus Asynchronous Timing 56F807 Technical Data Technical Data, Rev. 15 34 Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing 3.6 Reset, Stop, Wait, Mode Select, and Interrupt Timing Table 3-11 Reset, Stop, Wait, Mode Select, and Interrupt Timing1,5 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF Characteristic RESET Assertion to Address, Data and Control Signals High Impedance Minimum RESET Assertion Duration2 OMR Bit 6 = 0 OMR Bit 6 = 1 RESET Deassertion to First External Address Output Edge-sensitive Interrupt Request Width IRQA, IRQB Assertion to External Data Memory Access Out Valid, caused by first instruction execution in the interrupt service routine IRQA, IRQB Assertion to General Purpose Output Valid, caused by first instruction execution in the interrupt service routine IRQA Low to First Valid Interrupt Vector Address Out recovery from Wait State3 IRQA Width Assertion to Recover from Stop State4 Delay from IRQA Assertion to Fetch of first instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 Duration for Level Sensitive IRQA Assertion to Cause the Fetch of First IRQA Interrupt Instruction (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 Delay from Level Sensitive IRQA Assertion to First Interrupt Vector Address Out Valid (exiting Stop) OMR Bit 6 = 0 OMR Bit 6 = 1 Symbol tRAZ tRA 275,000T 128T tRDA tIRW tIDM 33T 1.5T 15T -- -- 34T -- -- ns ns ns ns ns 3-12 3-13 3-14 Min -- Max 21 Unit ns See Figure 3-12 3-12 tIG 16T -- ns 3-14 tIRI 13T -- ns 3-15 tIW tIF 2T -- ns 3-16 3-16 -- -- tIRQ -- -- tII -- -- 275,000T 12T ns ns 3-17 275,000T 12T ns ns 3-17 275,000T 12T ns ns 1. In the formulas, T = clock cycle. For an operating frequency of 80MHz, T = 12.5ns. 2. Circuit stabilization delay is required during reset when using an external clock or crystal oscillator in two cases: * After power-on reset * When recovering from Stop state 3. The minimum is specified for the duration of an edge-sensitive IRQA interrupt required to recover from the Stop state. This is not the minimum required so that the IRQA interrupt is accepted. 4. The interrupt instruction fetch is visible on the pins only in Mode 3. 5. Parameters listed are guaranteed by design. 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 35 RESET tRA tRAZ tRDA A0-A15, D0-D15 PS, DS, RD, WR First Fetch First Fetch Figure 3-12 Asynchronous Reset Timing IRQA, IRQB tIRW Figure 3-13 External Interrupt Timing (Negative-Edge-Sensitive) A0-A15, PS, DS, RD, WR tIDM IRQA, IRQB First Interrupt Instruction Execution a) First Interrupt Instruction Execution General Purpose I/O Pin tIG IRQA, IRQB b) General Purpose I/O Figure 3-14 External Level-Sensitive Interrupt Timing 56F807 Technical Data Technical Data, Rev. 15 36 Freescale Semiconductor Reset, Stop, Wait, Mode Select, and Interrupt Timing IRQA, IRQB tIRI A0-A15, PS, DS, RD, WR First Interrupt Vector Instruction Fetch Figure 3-15 Interrupt from Wait State Timing tIW IRQA tIF A0-A15, PS, DS, RD, WR First Instruction Fetch Not IRQA Interrupt Vector Figure 3-16 Recovery from Stop State Using Asynchronous Interrupt Timing tIRQ IRQA tII A0-A15 PS, DS, RD, WR First IRQA Interrupt Instruction Fetch Figure 3-17 Recovery from Stop State Using IRQA Interrupt Service RSTO tRSTO Figure 3-18 Reset Output Timing 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 37 3.7 Serial Peripheral Interface (SPI) Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic Cycle time Master Slave Enable lead time Master Slave Enable lag time Master Slave Clock (SCK) high time Master Slave Clock (SCK) low time Master Slave Data set-up time required for inputs Master Slave Data hold time required for inputs Master Slave Access time (time to data active from high-impedance state) Slave Disable time (hold time to high-impedance state) Slave Data Valid for outputs Master Slave (after enable edge) Data invalid Master Slave Rise time Master Slave Fall time Master Slave 1. Parameters listed are guaranteed by design. Table 3-12 SPI Timing1 Symbol tC 50 25 tELD -- 25 tELG -- 100 tCH 17.6 12.5 tCL 24.1 25 tDS 20 0 tDH 0 2 tA 4.8 tD 3.7 tDV -- -- tDI 0 0 tR -- -- tF -- -- Min Max -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns See Figure 3-19-3-22 3-22 ns ns 3-22 ns ns ns ns ns ns ns ns ns ns 3-19, 3-20, 3-21, 3-22 3-19, 3-20, 3-21, 3-22 3-22 15 15.2 4.5 20.4 -- -- 11.5 10.0 9.7 9.0 ns 3-22 ns ns ns ns ns ns ns ns ns 3-19, 3-20, 3-21, 3-22 3-19, 3-20, 3-21, 3-22 3-19, 3-20, 3-21, 3-22 3-19, 3-20, 3-21, 3-22 3-19, 3-20, 3-21, 3-22 3-22 56F807 Technical Data Technical Data, Rev. 15 38 Freescale Semiconductor Serial Peripheral Interface (SPI) Timing SS (Input) SS is held High on master tC tR tCL tCH tF tR tF SCLK (CPOL = 0) (Output) SCLK (CPOL = 1) (Output) tDH tDS tCL tCH MISO (Input) MSB in tDI Bits 14-1 tDV LSB in tDI(ref) MOSI (Output) Master MSB out tF Bits 14-1 Master LSB out tR Figure 3-19 SPI Master Timing (CPHA = 0) SS (Input) SS is held High on master tC tCL tF tR SCLK (CPOL = 0) (Output) tCH tF SCLK (CPOL = 1) (Output) tCL tCH tR tDS tDH MISO (Input) tDV(ref) MSB in tDI Bits 14-1 tDV LSB in tDI(ref) MOSI (Output) Master MSB out tF Bits 14- 1 Master LSB out tR Figure 3-20 SPI Master Timing (CPHA = 1) 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 39 SS (Input) tC tCL tF tR tELG SCLK (CPOL = 0) (Input) tELD tCH tCL SCLK (CPOL = 1) (Input) tA tCH tR tF tD MISO (Output) tDS Slave MSB out Bits 14-1 tDV tDH Slave LSB out tDI tDI MOSI (Input) MSB in Bits 14-1 LSB in Figure 3-21 SPI Slave Timing (CPHA = 0) SS (Input) tC tF tCL tCH tELD tCL tR SCLK (CPOL = 0) (Input) tELG SCLK (CPOL = 1) (Input) tDV tA tCH tF tR tD MISO (Output) tDS Slave MSB out Bits 14-1 tDV tDH Slave LSB out tDI MOSI (Input) MSB in Bits 14-1 LSB in Figure 3-22 SPI Slave Timing (CPHA = 1) 56F807 Technical Data Technical Data, Rev. 15 40 Freescale Semiconductor Quad Timer Timing 3.8 Quad Timer Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic Timer input period Timer input high/low period Timer output period Timer output high/low period 1. Table 3-13 Timer Timing1, 2 Symbol PIN PINHL POUT POUTHL Min 4T + 6 2T + 3 2T 1T Max -- -- -- -- Unit ns ns ns ns In the formulas listed, T = the clock cycle. For 80MHz operation, T = 12.5ns. 2. Parameters listed are guaranteed by design. Timer Inputs PIN PINHL PINHL Timer Outputs POUT POUTHL POUTHL Figure 3-23 Timer Timing 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 41 3.9 Quadrature Decoder Timing Table 3-14 Quadrature Decoder Timing1, 2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic Quadrature input period Quadrature input high/low period Quadrature phase period Symbol PIN PHL PPH Min 8T + 12 4T + 6 2T + 3 Max -- -- -- Unit ns ns ns 1. In the formulas listed, T = the clock cycle. For 80MHz operation, T=12.5ns. VSS = 0V, VDD = 3.0-3.6V, TA = -40 to +85C, CL 50pF. 2. Parameters listed are guaranteed by design. PPH PPH PPH PPH Phase A (Input) PHL PIN PHL Phase B (Input) PHL PIN PHL Figure 3-24 Quadrature Decoder Timing 56F807 Technical Data Technical Data, Rev. 15 42 Freescale Semiconductor Serial Communication Interface (SCI) Timing 3.10 Serial Communication Interface (SCI) Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic Baud Rate1 RXD2 Pulse Width TXD3 Pulse Width Symbol BR RXDPW TXDPW Min Max (fMAX*2.5)/(80) 1.04/BR 1.04/BR Unit Mbps ns ns Table 3-15 SCI Timing4 -- 0.965/BR 0.965/BR 1. fMAX is the frequency of operation of the system clock in MHz. 2. The RXD pin in SCI0 is named RXD0 and the RXD pin in SCI1 is named RXD1. 3. The TXD pin in SCI0 is named TXD0 and the TXD pin in SCI1 is named TXD1. 4. Parameters listed are guaranteed by design. RXD SCI receive data pin (Input) RXDPW Figure 3-25 RXD Pulse Width TXD SCI receive data pin (Input) TXDPW Figure 3-26 TXD Pulse Width 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 43 3.11 Analog-to-Digital Converter (ADC) Characteristics Table 3-16 ADC Characteristics Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, VREF = VDD-0.3V, ADCDIV = 4, 9, or 14, (for optimal performance), ADC clock = 4MHz, 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic ADC input voltages Resolution Integral Non-Linearity3 Differential Non-Linearity Monotonicity ADC internal clock5 Conversion range Conversion time Sample time Input capacitance Gain Error (transfer gain)5 Total Harmonic Distortion5 Offset Voltage5 Signal-to-Noise plus Distortion5 Effective Number of Bits5 Spurious Free Dynamic Range5 Bandwidth ADC Quiescent Current (each dual ADC) VREF Quiescent Current (each dual ADC) fADIC RAD tADC tADS CADI EGAIN THD VOFFSET SINAD ENOB SFDR BW IADC IVREF 0.5 VSSA -- -- -- 0.93 60 -90 55 9 65 -- -- -- Symbol VADCIN RES INL DNL Min 01 12 -- -- Typ -- -- +/- 2.5 +/- 0.9 GUARANTEED -- -- 6 1 5 1.00 64 -25 60 10 70 100 50 12 5 VDDA -- -- -- 1.08 -- +10 -- -- -- -- -- 16.5 mV -- bit dB KHz mA mA MHz V tAIC cycles6 tAIC cycles6 pF6 -- Max VREF2 12 +/- 4 +/- 1 Unit V Bits LSB4 LSB4 1. For optimum ADC performance, keep the minimum VADCIN value > 25mV. Inputs less than 25mV may convert to a digital output code of 0. 2. VREF must be equal to or less than VDDA and must be greater than 2.7V. For optimal ADC performance, set VREF to VDDA-0.3V. 3. Measured in 10-90% range. 4. LSB = Least Significant Bit. 5. Guaranteed by characterization. 6. tAIC = 1/fADIC 56F807 Technical Data Technical Data, Rev. 15 44 Freescale Semiconductor Controller Area Network (CAN) Timing . ADC analog input 3 1 2 4 1. Parasitic capacitance due to package, pin to pin, and pin to package base coupling. (1.8pf) 2. Parasitic capacitance due to the chip bond pad, ESD protection devices and signal routing. (2.04pf) 3. Equivalent resistance for the ESD isolation resistor and the channel select mux. (500 ohms) 4. Sampling capacitor at the sample and hold circuit. Capacitor 4 is normally disconnected from the input and is only connected to it at sampling time. (1pf) Figure 3-27 Equivalent Analog Input Circuit 3.12 Controller Area Network (CAN) Timing Table 3-17 CAN Timing2 Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL < 50pF, MSCAN Clock = 30MHz Characteristic Baud Rate Bus Wakeup detection 1 Symbol BRCAN T WAKEUP Min Max 1 Unit Mbps s -- 5 -- 1. If Wakeup glitch filter is enabled during the design initialization and also CAN is put into SLEEP mode then, any bus event (on MSCAN_RX pin) whose duration is less than 5 microseconds is filtered away. However, a valid CAN bus wakeup detection takes place for a wakeup pulse equal to or greater than 5 microseconds. The number 5 microseconds originates from the fact that the CAN wakeup message consists of 5 dominant bits at the highest possible baud rate of 1Mbps. 2. Parameters listed are guaranteed by design MSCAN_RX CAN receive data pin (Input) T WAKEUP Figure 3-28 Bus Wakeup Detection 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 45 3.13 JTAG Timing Operating Conditions: VSS = VSSA = 0 V, VDD = VDDA = 3.0-3.6 V, TA = -40 to +85C, CL 50pF, fOP = 80MHz Characteristic TCK frequency of TCK cycle time TCK clock pulse width TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO tri-state TRST assertion time DE assertion time operation2 Symbol fOP tCY tPW tDS tDH tDV tTS tTRST tDE Min DC 100 50 0.4 1.2 -- -- 50 4T Max 10 -- -- -- -- 26.6 23.5 -- -- Unit MHz ns ns ns ns ns ns ns ns Table 3-18 JTAG Timing1, 3 1. Timing is both wait state and frequency dependent. For the values listed, T = clock cycle. For 80MHz operation, T = 12.5ns. 2. TCK frequency of operation must be less than 1/8 the processor rate. 3. Parameters listed are guaranteed by design. tCY tPW VIH tPW VM TCK (Input) VM = VIL + (VIH - VIL)/2 VM VIL Figure 3-29 Test Clock Input Timing Diagram 56F807 Technical Data Technical Data, Rev. 15 46 Freescale Semiconductor JTAG Timing TCK (Input) tDS tDH TDI TMS (Input) TDO (Output) Input Data Valid tDV Output Data Valid tTS TDO (Output) tDV TDO (Output) Output Data Valid Figure 3-30 Test Access Port Timing Diagram TRST (Input) tTRST Figure 3-31 TRST Timing Diagram DE tDE Figure 3-32 OnCE--Debug Event 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 47 Part 4 Packaging 4.1 Package and Pin-Out Information 56F807 This section contains package and pin-out information for the 56F807. This device comes in two case types: low-profile quad flat pack (LQFP) or mold array process ball grid assembly (MAPBGA). Figure 4-1 shows the package outline for the LQFP case, Figure 4-2 shows the mechanical parameters for the LQFP case, and Table 4-1 lists the pinout for the LQFP case. Figure 4-3 shows the mechanical parameters for the MAPBGA case, and Table 4-2 lists the pinout for the MAPBGA package. SCLK SS MSCAN_RX VSS VDD MSCAN_TX CLKO VSS VCAPC2 TDO TDI TMS INDEX1 VDD HOME1 RXD0 TXD0 INDEX0 PHB0 PHA0 MOSI0 MISO0 PHB1 PHA1 HOME0 TCK TCS TRST TC1 TC0 TD3 TD2 TD1 TD0 ISA2 ISA1 ISA0 VPP VSS A0 A1 A2 A3 A4 A5 A6 A7 VDD A8 A9 A10 A11 A12 A13 A14 A15 VSS PS DS WR RD D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 VDD D11 D12 D13 D14 D15 GPIOB0 Orientation Mark Pin 1 121 DE ANB7 ANB6 ANB5 ANB4 ANB3 ANB2 ANB1 ANB0 VSSA VDDA VREF2 ANA7 ANA6 ANA5 ANA4 ANA3 ANA2 ANA1 ANA0 VSSA VDDA VREF RESET RSTO VDD VSS VDD EXTAL XTAL VSS VSS VDD VDDA VSSA EXTBOOT FAULTA3 FAULTA2 41 81 FAULTA1 FAULTA0 PWMA5 PWMA1 GPIOB2 GPIOB3 GPIOB4 GPIOB5 PWMB0 PWMB1 PWMB2 PWMB3 PWMB4 PWMB5 VDD ISB0 VCAPC1 ISB1 ISB2 VPP2 IRQA IRQB FAULTB0 FAULTB1 FAULTB2 FAULTB3 PWMA0 VSS GPIOB1 GPIOB6 GPIOB7 VSS GPIOD0 GPIOD1 GPIOD2 Figure 4-1 Top View, 56F807 160-pin LQFP Package 56F807 Technical Data Technical Data, Rev. 15 48 Freescale Semiconductor GPIOD3 GPIOD4 GPIOD5 TXD1 RXD1 PWMA2 PWMA3 PWMA4 Package and Pin-Out Information 56F807 160X 0.20 C A-B D D 6 D 2 D c GG b (b) A B SECTION G-G NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DATUMS A, B, AND D TO BE DETERMINED WHERE THE LEADS EXIT THE PLASTIC BODY AT DATUM PLANE H. 4. DIMENSIONS D1 AND E1 DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25mm PER SIDE. DIMENSIONS D1 AND E1 ARE MAXIMUM PLASTIC BODY SIZE DIMENSIONS INCLUDING MOLD MISMATCH. 5. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED THE MAXIMUM b DIMENSION BY MORE THAN 0.08mm. DAMBAR CAN NOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM SPACE BETWEEN A PROTRUSION AND AN ADJACENT LEAD IS 0.07mm. 6. EXACT SHAPE OF CORNERS MAY VARY. D1 2 D1 DETAIL F 4X 0.20 H A-B D 156X C SEATING PLANE 4X e e/2 160X E1 2 E 2 0.08 C e M MILLIMETERS DIM MIN MAX A --1.60 A1 0.05 0.15 A2 1.35 1.45 b 0.17 0.27 b1 0.17 0.23 c 0.09 0.20 c1 0.09 0.16 D 26.00 BSC D1 24.00 BSC e 0.50 BSC E 26.00 BSC E1 24.00 BSC L 0.45 0.75 L1 1.00 REF R1 0.08 --R2 0.08 0.20 S 0.20 -- 0 7 1 0 --2 11 13 3 11 13 0.08 2 1 R1 R2 H C A-B D A2 A 3 A1 S L (L1) DETAIL F 0.25 GAGE PLANE CASE 1259-01 ISSUE O Figure 4-2 160-pin LQFP Mechanical Information Please see www.freescale.com for the most current case outline. 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 49 E1 E c1 Table 4-1 56F807 LQFP Package Pin Identification by Pin Number Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 Signal Name A0 A1 A2 A3 A4 A5 A6 A7 VDD Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 Signal Name GPIOB1 GPIOB2 GPIOB3 GPIOB4 GPIOB5 GPIOB6 GPIOB7 VSS GPIOD0 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 TXD1 RXD1 PWMB0 PWMB1 PWMB2 PWMB3 PWMB4 PWMB5 VDD ISB0 VCAPC1 ISB1 ISB2 VPP2 IRQA IRQB Pin No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 Signal Name PWMA5 FAULTA0 FAULTA1 FAULTA2 FAULTA3 EXTBOOT VSSA VDDA VDD VSS VSS XTAL EXTAL VDD VSS VDD RSTO RESET VREF VDDA VSSA ANA0 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 VREF2 Pin No. 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 Signal Name DE VSS ISA0 ISA1 ISA2 TD0 TD1 TD2 TD3 TC0 TC1 TRST TCS TCK TMS TDI TDO VCAPC2 MSCAN_TX VDD VSS MSCAN_RX SS SCLK MISO MOSI PHA0 PHB0 INDEX0 HOME0 A8 A9 A10 A11 A12 A13 A14 A15 VSS PS DS WR RD D0 D1 D2 D3 D4 D5 D6 D7 56F807 Technical Data Technical Data, Rev. 15 50 Freescale Semiconductor Package and Pin-Out Information 56F807 Table 4-1 56F807 LQFP Package Pin Identification by Pin Number (Continued) Pin No. 31 32 33 34 35 36 37 38 39 40 Signal Name D8 D9 D10 VDD D11 D12 D13 D14 D15 GPIOB0 Pin No. 71 72 73 74 75 76 77 78 79 80 Signal Name FAULTB0 FAULTB1 FAULTB2 FAULTB3 PWMA0 VSS PWMA1 PWMA2 PWMA3 PWMA4 Pin No. 111 112 113 114 115 116 117 118 119 120 Signal Name VDDA VSSA ANB0 ANB1 ANB2 ANB3 ANB4 ANB5 ANB6 ANB7 Pin No. 151 152 153 154 155 156 157 158 159 160 Signal Name PHA1 PHB1 VDD INDEX1 HOME1 VPP VSS CLKO TXD0 RXD0 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 51 X Y D LASER MARK FOR PIN 1 IDENTIFICATION IN THIS AREA M K E NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSION b IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO DATUM PLANE Z. 4. DATUM Z (SEATING PLANE) IS DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 5. PARALLELISM MEASUREMENT SHALL EXCLUDE ANY EFFECT OF MARK ON TOP SURFACE OF PACKAGE. 0.20 13X e METALIZED MARK FOR PIN 1 IDENTIFICATION IN THIS AREA A B C S 14 13 12 11 10 9 6 5 4 3 2 1 MILLIMETERS DIM MIN MAX A 1.32 1.75 A1 0.27 0.47 A2 1.18 REF b 0.35 0.65 D 15.00 BSC E 15.00 BSC e 1.00 BSC S 0.50 BSC S 13X D E F G H J K L M N 160X 5 A A2 0.30 Z e A1 Z 4 0.15 Z ROTATED 90 CLOCKWISE DETAIL K 3 160X P b 0.30 Z X Y 0.10 Z VIEW M-M CASE 1268-01 ISSUE O Figure 4-3 160 MAPBGA Mechanical Information Please see www.freescale.com for the most current case outline. 56F807 Technical Data Technical Data, Rev. 15 52 Freescale Semiconductor Package and Pin-Out Information 56F807 Table 4-2 160 MAPBGA Package Pin Identification by Pin Number Solder Ball C3 B2 D3 C2 B1 D2 C1 D1 E3 E2 E1 F3 F2 F1 G3 G2 G1 F4 G4 H4 J4 K4 Signal Name A0 A1 A2 A3 A4 A5 A6 A7 Solder Ball N4 P4 M4 L5 N5 P5 K5 N6 L6 K6 P6 N7 L7 P7 K7 L8 K8 P8 L9 N8 P14 M13 Signal Name GPIOB5 GPIOB6 GPIOB7 Solder Ball K12 K13 L14 K11 K14 J13 J12 J14 J11 H13 H12 H14 H11 G12 G11 G14 B13 A14 B12 A13 A12 B11 Signal Name VSSA VDDA VDD VSS VSS XTAL EXTAL Solder Ball E10 D9 B9 E9 A9 D8 B8 A8 E8 D7 E7 D6 H1 H2 J3 J1 J2 K3 K1 L1 K2 L3 Signal Name TC1 TRST TCS TCK TMS TDI TDO VCAPC2 MSCAN_TX VSS GPIOD0 GPIOD1 GPIOD2 GPIOD3 GPIOD4 GPIOD5 TXD1 RXD1 PWMB0 PWMB1 PWMB2 PWMB3 PWMB4 PWMB5 VDD VSS VDD RSTO RESET VREF VDD A8 A9 A10 A11 A12 A13 A14 A15 VDD VSS MSCAN_RX D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 VDDA VSSA ANA0 DE VSS PS DS WR RD VSS ISA0 ISA1 ISA2 TD0 VDD ISB0 PWMA5 FAULTA0 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 53 Table 4-2 160 MAPBGA Package Pin Identification by Pin Number (Continued) Solder Ball P1 N3 P2 P3 N2 M3 L4 K10 K9 P9 L10 N9 P10 P11 N10 L11 M11 P12 Signal Name GPIOB1 GPIOB2 GPIOB3 GPIOB4 D14 D15 GPIOB0 VCAPC1 ISB1 ISB2 VPP2 IRQA IRQB FAULTB0 FAULTB1 FAULTB2 FAULTB3 PWMA0 Solder Ball L12 N14 L13 M14 N11 P13 N12 N13 M12 F11 G13 F12 F14 E11 F13 E12 E14 E13 Signal Name FAULTA1 FAULTA2 FAULTA3 EXTBOOT Solder Ball A11 D10 B10 A10 D14 D11 D12 D13 C14 C13 C11 B14 C12 A7 E5 B7 A6 E6 Signal Name TD1 TD2 TD3 TC0 Solder Ball M1 L2 N1 M2 D5 B6 A5 E4 B5 A4 D4 C4 B4 A2 B3 A1 A3 H3 Signal Name VDD D11 D12 D13 PHB0 INDEX0 HOME0 PHA1 PHB1 VSS PWMA1 PWMA2 PWMA3 PWMA4 ANA1 ANA2 ANA3 ANA4 ANA5 ANA6 ANA7 VREF2 VSSA ANA8 ANA9 ANA10 ANA11 ANA12 ANA13 ANA14 ANA15 SS SCLK MISO MOSI PHA0 VDD INDEX1 HOME1 VPP CLKO TXD0 RXD0 VSS D0 VDDA 56F807 Technical Data Technical Data, Rev. 15 54 Freescale Semiconductor Thermal Design Considerations Part 5 Design Considerations 5.1 Thermal Design Considerations An estimation of the chip junction temperature, TJ, in C can be obtained from the equation: Equation 1: T J = T A + ( P D x R JA ) Where: TA = ambient temperature C RJA = package junction-to-ambient thermal resistance C/W PD = power dissipation in package Historically, thermal resistance has been expressed as the sum of a junction-to-case thermal resistance and a case-to-ambient thermal resistance: Equation 2: R JA = R JC + R CA Where: RJA = package junction-to-ambient thermal resistance C/W RJC = package junction-to-case thermal resistance C/W RCA = package case-to-ambient thermal resistance C/W RJC is device-related and cannot be influenced by the user. The user controls the thermal environment to change the case-to-ambient thermal resistance, RCA. For example, the user can change the air flow around the device, add a heat sink, change the mounting arrangement on the Printed Circuit Board (PCB), or otherwise change the thermal dissipation capability of the area surrounding the device on the PCB. This model is most useful for ceramic packages with heat sinks; some 90% of the heat flow is dissipated through the case to the heat sink and out to the ambient environment. For ceramic packages, in situations where the heat flow is split between a path to the case and an alternate path through the PCB, analysis of the device thermal performance may need the additional modeling capability of a system level thermal simulation tool. The thermal performance of plastic packages is more dependent on the temperature of the PCB to which the package is mounted. Again, if the estimations obtained from RJA do not satisfactorily answer whether the thermal performance is adequate, a system level model may be appropriate. Definitions: A complicating factor is the existence of three common definitions for determining the junction-to-case thermal resistance in plastic packages: * Measure the thermal resistance from the junction to the outside surface of the package (case) closest to the chip mounting area when that surface has a proper heat sink. This is done to minimize temperature variation across the surface. 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 55 * * Measure the thermal resistance from the junction to where the leads are attached to the case. This definition is approximately equal to a junction to board thermal resistance. Use the value obtained by the equation (TJ - TT)/PD where TT is the temperature of the package case determined by a thermocouple. The thermal characterization parameter is measured per JESD51-2 specification using a 40-gauge type T thermocouple epoxied to the top center of the package case. The thermocouple should be positioned so that the thermocouple junction rests on the package. A small amount of epoxy is placed over the thermocouple junction and over about 1mm of wire extending from the junction. The thermocouple wire is placed flat against the package case to avoid measurement errors caused by cooling effects of the thermocouple wire. When heat sink is used, the junction temperature is determined from a thermocouple inserted at the interface between the case of the package and the interface material. A clearance slot or hole is normally required in the heat sink. Minimizing the size of the clearance is important to minimize the change in thermal performance caused by removing part of the thermal interface to the heat sink. Because of the experimental difficulties with this technique, many engineers measure the heat sink temperature and then back-calculate the case temperature using a separate measurement of the thermal resistance of the interface. From this case temperature, the junction temperature is determined from the junction-to-case thermal resistance. 5.2 Electrical Design Considerations CAUTION This device contains protective circuitry to guard against damage due to high static voltage or electrical fields. However, normal precautions are advised to avoid application of any voltages higher than maximum rated voltages to this high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate voltage level. Use the following list of considerations to assure correct operation: * * Provide a low-impedance path from the board power supply to each VDD pin on the controller, and from the board ground to each VSS pin. The minimum bypass requirement is to place 0.1 F capacitors positioned as close as possible to the package supply pins. The recommended bypass configuration is to place one bypass capacitor on each of the VDD/VSS pairs, including VDDA/VSSA. Ceramic and tantalum capacitors tend to provide better performance tolerances. 56F807 Technical Data Technical Data, Rev. 15 56 Freescale Semiconductor Electrical Design Considerations * * * * Ensure that capacitor leads and associated printed circuit traces that connect to the chip VDD and VSS pins are less than 0.5 inch per capacitor lead. Bypass the VDD and VSS layers of the PCB with approximately 100 F, preferably with a high-grade capacitor such as a tantalum capacitor. Because the controller's output signals have fast rise and fall times, PCB trace lengths should be minimal. Consider all device loads as well as parasitic capacitance due to PCB traces when calculating capacitance. This is especially critical in systems with higher capacitive loads that could create higher transient currents in the VDD and VSS circuits. Take special care to minimize noise levels on the VREF, VDDA and VSSA pins. Designs that utilize the TRST pin for JTAG port or OnCE module functionality (such as development or debugging systems) should allow a means to assert TRST whenever RESET is asserted, as well as a means to assert TRST independently of RESET. TRST must be asserted at power up for proper operation. Designs that do not require debugging functionality, such as consumer products, TRST should be tied low. Because the Flash memory is programmed through the JTAG/OnCE port, designers should provide an interface to this port to allow in-circuit Flash programming. * * * 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 57 Part 6 Ordering Information Table 6-1 lists the pertinent information needed to place an order. Consult a Freescale Semiconductor sales office or authorized distributor to determine availability and to order parts. Table 6-1 56F807 Ordering Information Part 56F807 56F807 Supply Voltage 3.0-3.6 V 3.0-3.6 V Package Type Low-Profile Quad Flat Pack (LQFP) Mold Array Process Ball Grid Array (MAPBGA) Pin Count 160 160 Ambient Frequency (MHz) 80 80 Order Number DSP56F807PY80 DSP56F807VF80 56F807 56F807 3.0-3.6 V 3.0-3.6 V Low-Profile Quad Flat Pack (LQFP) Mold Array Process Ball Grid Array (MAPBGA) 160 160 80 80 DSP56F807PY80E* DSP56F807VF80E* *This package is RoHS compliant. 56F807 Technical Data Technical Data, Rev. 15 58 Freescale Semiconductor Electrical Design Considerations 56F807 Technical Data Technical Data, Rev. 15 Freescale Semiconductor 59 How to Reach Us: Home Page: www.freescale.com E-mail: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 +1-800-521-6274 or +1-480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064, Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp. Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. This product incorporates SuperFlash(R) technology licensed from SST. (c) Freescale Semiconductor, Inc. 2005. All rights reserved. DSP56F807 Rev. 15 01/2007 |
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